NSITEXE Achieves First-Pass Silicon Success for High-Performance Data Flow Processor-based SoC Test Chip Using DesignWare IP

MOUNTAIN VIEW, Calif., Oct 28, 2019

Highlights:

• DesignWare Controller and PHY IP for PCI Express and LPDDR accelerates development of the advanced data flow processor-based SoC
• Embedded Memories and Logic Libraries offer options for high-temperature PVT corners for superior, power, performance, and area
• STAR Memory System and STAR Hierarchical System helps allow efficient test, repair, and diagnostics of embedded memories

Synopsys, Inc. (Nasdaq: SNPS) today announced that NSITEXE, a Denso Group Company, achieved first-pass silicon success for its high-performance Data Flow Processor (DFP)-based SoC test chip using Synopsys' DesignWare^® Interface and Foundation IP portfolios. With Synopsys' silicon-proven DesignWare IP, NSITEXE met the advanced functionality, processing, performance, and testability requirements of its DFP-based SoC. NSITEXE's DFP-based SoC combines both a CPU and a GPU to process large and complex datasets for parallel data management with power-efficient parallelism and quality.

"To implement state-of-the-art capabilities in our SoC, we needed a broad range of IP that met our aggressive power, performance, and area requirements," said Hideki Sugimoto, chief technology officer at NSITEXE. "After evaluating Synopsys' comprehensive portfolio of interface IP, we were confident that with Synopsys' high-quality DesignWare IP we are able to accelerate our project schedule and achieve first-pass silicon success."

Synopsys' silicon-proven DesignWare IP for PCI Express 3.0 delivers low latency and high performance for efficient system throughput in advanced designs. The robust architecture of the DesignWare LPDDR4 IP enables fast access to the DRAM with high data bandwidth and low power. The DesignWare Embedded Memories and Logic Libraries deliver the industry's only foundation IP solution to offer options for high-temperature process, voltage, and temperature (PVT) corners, enabling designers to achieve the best combination of performance, power, and area. For comprehensive test coverage, Synopsys' STAR Hierarchical System and STAR Memory System initialize the LPDDR PHY and perform high-quality user-programmable tests on the external memory and interconnect. The STAR Hierarchical System's Measurement Unit performs accurate on-chip characterization for critical phase-locked-loop (PLL) clock measurement without the need for additional fractional PLLs or high-frequency clock sources.

"SoCs for advanced applications are growing in complexity and require a range of IP to implement the necessary functionality," said John Koeter, vice president of marketing for IP at Synopsys. "By providing the industry's broadest IP portfolio, Synopsys is enabling innovative companies like NSITEXE to meet their advanced design needs, while accelerating the development of their automotive SoCs."

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